1. Technical Field
Example embodiments relate generally to a clock signal processor, and more particularly to a clock signal processor executing a duty cycle correction and a non-volatile memory device including the same.
2. Discussion of the Related Art
Recently, components, such as a processor and a memory included in a general electronic device, transceive data with each other in synchronization with clock signals. However, errors may occur when the data are transceived between the components if a duty cycle error occurs due to the mismatch in length between a logic low level duration and a logic high level duration of the clock signal.
For instance, in the case of a DDR (double data rate) memory, the data are transceived at every rising edge and falling edge of the clock signal. If the duty cycle error occurs in the clock signal, a data transceiving interval may not be constantly maintained, so an error may occur when the data are transceived between the DDR memory and the processor.
Thus, it may be necessary to execute a duty cycle correction (DCC) with maintaining performance of the DDR non-volatile memory device.